Programming Languages, Architecture and Compilers Education Laboratory
DCEIL: Distributed Community Detection with the CEIL Score Akash Jain, Rupesh Nasre, and Ravindran Balaraman To appear in the 18th IEEE Conference on High Performance Computing and Communications (HPCC 2017), December 18-20, 2017, Bangkok, Thailand
FatCBST: Concurrent Binary Search Tree with Fatnodes Praveen Alapati, Venkata Kalyan Tavva and Madhu Mutyam To appear in the 18th IEEE Conference on High Performance Computing and Communications (HPCC 2017), December 18-20, 2017, Bangkok, Thailand
DomLock: A New Multi-Granularity Locking Technique for Hierarchies Saurabh Kalikar and Rupesh Nasre To appear in ACM Transactions on Parallel Computing, 2017
Concurrent Treaps Praveen Alapati, S R Swamy Saranam and Madhu Mutyam To appear in ICA3PP UCER 2017, August 21-23, 2017, Helsinki, Finland
Optimizing Recursive Task Parallel Programs Suyash Gupta, Rahul Shrivastava and V Krishna Nandivada International Conference on Supercomputing, June 14-16, 2017, Chicago, USA
Identifying Use-After-Free Variables in Fire-and-Forget Tasks Jyothi Krishna V S and Vassily Litvinov Chapel Implementers and Users Workshop, June 2-3, 2017, Orlando, Florida, USA
Automatic Code Generation for Graph Algorithms on GPUs Shashidhar G and Rupesh Nasre International Workshop on Languages and Compilers for Parallel Computing (LCPC), September 28-30, 2016, Rochester, NY, USA
EagerMerge: An Optimistic Technique for Efficient Points-to Analysis Sudhir Samrit and Rupesh Nasre International Symposium on Software Testing and Analysis (ISSTA), July 18-20, 2016, Germany
Improved MHP Analysis Aravind Sankar, Soham Chakraborty, V Krishna Nandivada International Conference on Compiler Construction (CC), March 17-18, 2016, Barceona, Spain
CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection Router Gnaneswara Rao Jonna, Vamana Murthi Thuniki and Madhu Mutyam International Conference on Architecture of Computing Systems (ARCS), April 4-7, 2016, Nuremberg, Germany
GPU Centric Extensions for Parallel Strongly Connected Components Computation Shrinivas Devshatwar, Madhur Amilkanthwar and Rupesh Nasre GPGPU 2016, March 12, 2016, Barcelona, Spain
DomLock: A New Multi-Granularity Locking Technique for Hierarchies Saurabh Kalikar and Rupesh Nasre Principles and Practice of Parallel Programming (PPoPP), March 12-16, 2016, Barcelona, Spain
PBC: Prefetched Block Compaction K. Raghavendra, Biswabandan Panda and Madhu Mutyam IEEE Transactions on Computers, 2015
MBZip: A Case for Compressing Multiple Data Blocks K. Raghavendra, Biswabandan Panda and Madhu Mutyam International Conference on Parallel Architectures and Compilation Techniques (PACT), October 18-21, 2015, San Franciso
Efficient online cycle detection technique combining with Steensgaard points-to information Fei Lui, Bixin Li and Rupesh Nasre Journal of Software: Practice and Experience, 2015
SkipCache: Application Aware Cache Management for Chip Multi-Processors Tripti S. Warrier, K. Raghavendra and Madhu Mutyam IET Computers & Digital Techniques(CDT), pp. 293-299, 2015
Unique Worker model for OpenMP Raghesh Aloor and V Krishna Nandivada International conference on Supercomputing (ICS), pp. 47-56, June 8-10, 2015, Newport Beach, CA, USA
Patent: Systems and methods for automatically optimizing high performance computing programming languages (US patent no: 8924946) Ganesh Bikshandi, V Krishna Nandivada, Igor Peshansky and Vijay Saraswat
Loop tiling in the presence of exceptions Abhilash Bhandari and V Krishna Nandivada European Conference on Object-Oriented Programming (ECOOP), pp. 124-128, July 5-10, 2015, Prague, Czech Republic
Lexical State Analyzer for JavaCC grammars K Gupta and V K Nandivada Software: Practice and Experience, 2015
EFGR: An Enhanced Fine Grain Granularity Refresh Feature for High Performance DDR4 DRAM Devices T.V. Kalyan, K. Ravi, and Madhu Mutyam 10th HiPEAC Conference, January 19-21, 2015, Amsterdam, Netherlands
IMSuite: A Benchmark Suite for Simulating Distributed Algorithms Suyash Gupta and V Krishna Nandivada Journal of Parallel and Distributed Computing, 2013
SFFMap: Set-First Fill Mapping for an Energy Efficient Pipelined Date Cache Pritam Majumder, Venkata Kalyan T and Madhu Mutyam IEEE International Conference on Computer Design (ICCD), pp. 104-109, 2014
EFGR: An Enhanced Fine Granularity Refresh Feature for High Performance DDR4 DRAM Devices Venkata Kalyan T, Ravi Kasha and Madhu Mutyam ACM Transactions on Architecture and Code Optimization (TACO), pp. 31:1-31:26, 2014
Implementation and Analysis of History Based Output Channel Selection Function for Adaptive Routers in Mesh NoCs John Jose and Madhu Mutyam ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 35:1-35:22, 2014
Auto-Parallelization of Data Structure Operations for GPUs Rupesh Nasre International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES), pp. 7:1-7:10, October 12-17, 2014, New Delhi, India
Data Remapping for an Energy Efficient Burst Chop in DRAM Memory Systems Sudharsan J, Venkata Kalyan T, and Madhu Mutyam ACM Student Research Competition (SRC), International Conference on Parallel Architectures and Compilation Techniques (PACT), August 24-27, 2014, Edmonton, Canada
Using Packet Information for Efficient Communication in NoCs Prasanna Venkatesh and Madhu Mutyam International Symposium on Networks-on-Chip (NOCS), pp. 43-150, September 17-19, 2014, Ferrera, Italia
Improving Fairness in Memory Scheduling Using a Team of Learning Automata Aditya Kajwe and Madhu Mutyam The Memory Forum, Co-located with ISCA, June 14, 2014, Minneapolis, Minnesota.
Push-Pull Constraint Graph for Efficient Points-to Analysis Bollu Ratnakar and Rupesh Nasre International Symposium on Memory Management (ISMM), pp. 25-33, June 12, 2014, Edinburgh, Scotland, UK.
Patent: Model, System and Program Storage Device for automatic incremental learning of Programming language grammar (US patent no : 8676826) V Krishna Nandivada, Pankaj Dhoolia, Mangala Gowri, and Diptikalyan Saha
Patent: System and Method for Dynamic Code Analysis in presence of the "table processing" idiom (US patent no : 8583965) V Krishna Nandivada, Pankaj Dhoolia, Mangala Gowri, and Diptikalyan Saha
Patent: Method, System and Program Storage Device that Provide for Automatic Programming Language Grammar Partitioning (US patent no : 8516457) V Krishna Nandivada, Pankaj Dhoolia, Mangala Gowri, and Diptikalyan Saha
SAMO: Store Aware Memory Optimizations. Raghavendra, Tripti Warrier, and Madhu Mutyam ACM International Conference on Computing Frontiers (CF), pp. 33:1-33:10, May 20-22, 2014, Cagliari, Italy
Improved Bitwidth-Aware Variable Packing. V Krishna Nandivada, Rajkishore Barik High Performance and Embedded Architecture and Compilation conference (HiPEAC), Jan 20-22, 2014, Vienna, Austria.
Minimally Bufferred Single-Cycle Deflection Router for Mesh NoCs. Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam International Conference on Design, Automation & Test in Europe (DATE), Mar 24-28, 2014, Dresden, Germany(accepted as a poster).
Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time. T.V. Kalyan, K. Ravi, Madhu Mutyam 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 598-603, Jan 20-23, 2014, Singapore.
SLIDER: Smart Late Injection DEflection Router for Mesh NoCs Bhawna Nayak, John Jose, Madhu Mutyam 31st IEEE International Conference on Computer Design (ICCD), pp. 377-383, Oct 6-9, 2013, Asheville, NC, USA.
Improved Bitwidth-Aware Variable Packing V K Nandivada, R Barik ACM Transactions on Architecture and Code Optimization (TACO), pp. 16:1-16:22, 2013
A Transformation Framework for Optimizing Task-Parallel Programs. V. Krishna Nandivada, Jun Shirako, Jisheng Zhao, Vivek Sarkar ACM Trans. Program. Lang. Syst. 35(1) 3, 2013
An Application-Aware Cache Replacement Policy for Last-Level Caches Tripti Warrier, B. Anupama, Madhu Mutyam ARCS 2013, pp. 207-219, 2013
DeBAR: deflection based adaptive router with minimal buffering John Jose, Bhawna Nayak, Kranthi Kumar, Madhu Mutyam DATE 2013, pp. 1583-1588, 2013
Fibonacci Codes for Crosstalk Avoidance Madhu Mutyam IEEE Trans. VLSI Syst. 20(10), pp. 1899-1903, 2012